Vietnam IT Development Group is looking to recruit 30 Engineers to work for companies located in Ho Chi Minh City, Da Nang and Hanoi
Salary between US$18K to US$36K
IC Layout Design Engineers
Candidate must possess at least a Bachelor’s Degree in Engineering (Electrical/Electronic) or equivalent.
Proficiency in IC layout design, IC layout verification, 24nm and below. Fluent in IC layout tools such as Cadence Virtuoso, and Calibre for DRC/LVS verifications.
A minimum of 2 year(s) of recent working experience in IC layout Design is required for this position.
Place and Route Engineer
Candidate should be experienced in Physical Design or Place and Route, including hands-on experience with one or more of the following tools: Preferably Synopsys (IC Compiler, Physical Compiler), or Cadence (SoC Encounter)
Experienced in Clock synthesis, and Timing Optimization, Timing/Signal Integrity Closure, and DFM Closure.
Minimum of 3 years industry experience in Physical design, including floor planning, Place and Route.
FOR MORE INFORMATION, PLEASE CONTACT:
MR. TRUNG TRINH, MANAGING PARTNER
Vietnam Resource & IT Development Group
189 W. Santa Clara St., San Jose, CA ̣̀95113
Tel.: 888-665-7749 &202-271-8200